The present invention relates to a method of programming a flash memory device. More particularly, the present invention relates to a method of programming which reduces a threshold voltage imbalance due to interference effects in the flash memory device.
Recently, the demand has increased for a non-volatile memory device which electrically programs and erases data, and does not require a refresh function for periodically rewriting data.
In addition, high integration techniques for a memory device have been studied so as to develop a high capacity memory device (e.g., flash memory device).
Generally, a flash memory device is divided into a NAND flash memory and a NOR flash memory. In the NOR flash memory, each of the memory cells is connected independently to a bit line and a word line, and so the NOR flash memory has excellent random access time. Whereas, in the NAND flash memory, only one contact is required for one cell string because memory cells are connected in series, and so the NAND flash memory has excellent characteristics for integration. Accordingly, the NAND flash memory has been generally employed in high density flash memory.
Recently, multi-bit cells for storing a plurality of data bits in one memory cell have been actively studied so as to enhance the degree of integration of the above flash memory. This memory cell is referred to as a multi-level cell (hereinafter, referred to as “MLC”). A memory cell for storing one data bit is referred to as a single level cell (SLC).
Since the MLC has at least four threshold voltage levels compared to an SLC which has two threshold voltage levels, the MLC can increase the number of bits by two or more times over the SLC.
On the other hand, it is important to reduce a change in the threshold voltage of a cell so as to embody the MLC. Here, one of the causes for the change is an interference effect due to capacitance between cells.
FIG. 1 is a view illustrating a threshold voltage distribution related to a conventional method of programming in a flash memory device.
Generally, a memory cell array included in the flash memory device has a cell string structure in which memory cells are connected in series, wherein the memory cells are connected to an even bit line or an odd bit line. Here, the odd bit line is adjacent to the even bit line.
In a program operation of the flash memory device, a first memory cell is programmed by applying a program voltage (e.g., 15V) to a word line of the first memory cell connected to the even bit line, and so the first memory cell has a threshold voltage distribution as shown in A of FIG. 1.
Subsequently, a second memory cell connected to the odd bit line adjacent to the first memory cell is programmed by applying the program voltage (e.g., 15V) to a word line of the second memory cell, and so the second memory cell has a threshold voltage distribution as shown in A′ of FIG. 1. In this case, the threshold voltage distribution of the first memory cell is shifted from A into B due to the interference effect when the second memory cell is programmed.
This change of the threshold voltage distribution deteriorates program characteristics of the flash memory device. Specially, sensing margin is reduced due to the change of the threshold voltage distribution in the MLC flash memory device.